Monday, August 2, 2010

SEMICON West meeting, speaker 2: Pete Singer on semiconductor fab trends

Editor in chief Pete Singer introduced technology trends in semiconductors at the breakfast meeting held during SEMICON West. Following are some of the key points and slides from his talk.

The semiconductor industry continues to push to smaller dimensions to gain more functionality in a smaller space. There’s also a drive to increase transistor performance and speed, while also reducing energy consumption. The requires more complicated transistor structures, such as FinFETS, and the use of new materials. 3D integration and advanced packaging strategies (such as package on package) are also seen as another way to put more functionality into a smaller space.

The conventional wisdom is that semiconductor scaling will continue at the traditional pace defined by Moore’s Law well into the future. 32nm devices are now in volume production and the industry is on track to move to the 22nm node in 2011. That will be followed by 15nm in the 2014-15 timeframe and the 11nm node in 2017-18. Further scaling to 8 and 5nm nodes will occur beyond 2020, perhaps enabled by silicon nanowires or other nanotechnology. What could derail this plan is the lack of a suitable lithographic toolset, but most people that EUV will be ready in time. What’s not clear is how the development of next generation technology will be funded. Equipment and materials suppliers have had to “reset” their R&D spending due to the financial crisis, so it’s likely that consortia and joint development activities will take on greater importance moving forward. At the same time, while some companies such as Intel are expected to relentlessly continue scaling, analysts are predicting a bifurcation in the industry where the majority of companies will be able to use older, larger-dimension technology to successfully meet market requirements.

It should be noted that new technologies are not necessarily more expensive. Research is clearly focused on finding lower cost solutions. Although EUV now appears to be the technology of choice for semiconductor lithography, despite its high cost and need for further development of mask and inspection techniques, a group of researchers are working to make multiple-column e-beam (MEB) lithography a reality. Similarly, plasma doping is less expensive that traditional ion implant and provides better device performance as well.

While scaling is often referred to as "More Moore," the term “More than Moore” has also come into vogue to describe this trend which goes beyond simple scaling. MEMS that integrate a microcontroller, sensor, energy harvesting devices and wireless networking are perhaps the best examples. “Functions initially fulfilled by non-CMOS dedicated technologies may eventually be integrated onto a CMOS SoC, using mixed technologies derived from core CMOS,” notes the ITRS. “Consequently, the partitioning of system-level functions between and within SoC and SiP is likely to be dynamic over time. This will require innovations in cross-disciplinary fields, such as nano-electronics, nano-thermomechanics, nano-biology, extremely parallel software, etc.”

Also check out IC Insights analyst Bill McClean's talk from the breakfast here:

Email Pete Singer at to view slide and get more in-depth information on his talk.

No comments:

Post a Comment