Rajaran Pendse, VP of the Technical Marketing Group at STATSChipPAC, told MEPTEC lunch forum attendees (6/8/11, Biltmore Hotel, Santa Clara, CA) that packaging technology and functional integration have progressed on three parallel fronts: package level, wafer level (fan-in/fan-out WLP), and at the silicon level (TSV). “There is a convergence towards silicon and wafer level approaches driven by I/O density trends,” said Pendse.
The company is already in HVM with standard eWLB technology (embedded wafer-level ball grid array) – a fan-out wafer-level technology that Pendse says is a breakthrough in terms of high routing density, low parasitics, and small form factors. The cost efficiency comes from the elimination of substrates, bumping, and underfill – the limiting factors in flip-chip packaging. Pendse also described work that the company is doing on more advanced versions process.
The process flow for eWLB comprise four basic steps: reconstitution of dies to an “artificial” wafer, redistribution, ball application and singulation, and test/route/scan/pack. To determine whether or not using eWLB will be cost-effective, the company has developed a design metric called “fan-out ratio” (FR). [It’s defined as: (I/O density of the die-substrate)/(I/O density of substrate-PCB).] When FR<1, the design calls for using WLCSP as the solution; when FR is between 1 and 3, the design calls for using eWLB; and when FR>3, the solutions should be either fcFBGA or fcBGA. “We have used FR as a parameter to define the application space and cross-over point among different packaging choices,” noted Pendse. (Debra Vogler)