The long-discussed and controversial 450mm wafer-size transition got a significant reality check with five of the biggest global chipmakers putting their skin in the game. 450mm's Original Three (Intel, Samsung, and TSMC), now joined by IBM and GlobalFoundries creating a "Global 450 Consortium", say they will spend $4.4B over the next five years for two chipmaking development projects spanning several sites in New York State. A big chunk of that will go toward proving out 450mm manufacturing work, that ultimately "may facilitate the possibility of building a 450mm plant in New York state" (note the double-noncommittal). The rest of the money will go toward 20nm/14nnm development work for IBM and partners.
This story is still taking shape, and we're still talking with sources to fill out the entire picture, but here's what we know so far (and we'll keep updating as we learn more):
-- Who's doing what? No details were provided about how the $4.4B is being split up: 1) between the 450mm work and IBM et al.'s 20nm/14nm development, or 2) among individual 450mm participants. All of the stated destinations in NY State for the investments are facilities owned by CNSE (Albany Nanotech, Canandaigua), IBM (Yorktown Heights and East Fishkill), or SUNY (Utica). CNSE will get $400M from the state over five years, including $100M for "energy efficiency and low-cost energy allowance."
Slides from CNSE execs over the past few months show a new "Nanofab" complex (dubbed "X" or "West") on the drawing board, with proposed 450K sq. ft. footprint including 45K sq. ft for cleanrooms. That's almost twice the size of CNSE's two major sites across the street: two-year-old Nanofab East, and six-year-old Nanofab North (home to CNSE's EUV alpha tool). This could be where the 450mm work takes place; we'll be talking with CNSE tomorrow (Weds. 9/28) for more information.
That $4.4B won't answer every 450mm production question, but equipment will be installed and "everyone will get to kick the tires, work on how to improve productivity, and jointly develop what the 450mm equipment should look like," explained Gartner research VP Dean Freeman. "It might be enough for the initial C&F to be done and prove out some of the economics." Specific goals will be to "learn things about how to boost plasma densities, improve wafer thickness uniformity, and improve system throughput of the area based equipment," he noted.
-- What about existing 450mm pilot-line efforts? Earlier this year, TSMC's Morris Chang was very clear about the foundry's 450mm plans: a pilot line at Fab 12 Phase VI starting with 20nm process technology, timed around 2013/2014, and a production line following around 2015/2016, a TSMC spokesperson reiterated that timeline to SST (adding that the production line would be in Fab 15). It is still unclear whether TSMC would continue to pursue its own in-house 450mm pilot line at the same time as this new group in New York. [Update 9/29: That same TSMC spokesperson pointed out that the Albany 450mm line will be consortium-run and is not considered a TSMC line, but said "maybe the timing will coincide with each other, or be very close."] Also note that Intel says it will make this its "450mm East Coast Headquarters," a qualification that implies a future West Coast operation too. The company's D1X fab on the West Coast, which was said to be built with 450mm in mind, probably will be for final work, not initial pilot-line stuff.
That said, more than likely this 450mm pilot line will go the way all such technology partnerships go: frenemies working together precompetitively, then taking the technologies back home to tinker for their own production. "While Intel will have folks on the East Coast, you can bet when the time comes you will see D1X with some 450mm equipment," said Freeman. Expect the same for TSMC, Samsung, and apparently GlobalFoundries and even IBM.
-- Who's missing? Note the "Global 450 Consortium" is comprised of private funds, and makes no mention of actual industry "consortia." IMEC's 300mm cleanroom was upgraded to be "450mm-ready" -- if this new 450mm thrust is chipmaker-only, where does that leave IMEC's efforts? "Companies that are not invited to the consortia party, will need to find a place to do the 450mm development work; that place will likely be IMEC," noted Freeman. The EU seeing 450mm as a possible route to become competitive in the semiconductor industry again, and "there is a lot of advanced transistor work that needs to take place," he added.
[Updated 9/29: ] SEMATECH/ISMI had been ramping its own early-work 450mm program, and this year ISMI received approval for NY state funding for 450mm development at Albany CNSE. At this summer's SEMICON West it said 10 tools were either installed or on order, and that "pilot line evaluations show 'low risk.'" Some 450mm equipment already in place at Albany CNSE are tools for lot sorting, wet cleans (a SSEC 3400 tool directly in front of the NanoFab North cleanroom viewing hallway), bare wafer defect detection, wafer edge inspection, and FOUP washing. "Our program is now a part of the new initiative, which will build on and expand our efforts," a SEMATECH spokesperson said, but noted that the actual location of 450mm tools hasn't been determined.
The aforementioned production gains from 450mm also would be very attractive given the relentless cost pressures and volumes required in DRAM. Freeman expressed surprise "that Toshiba is not yet a part of this" 450mm consortium. (Also not mentioned: Hynix or Elpida/Rexchip.)
-- What's the 450mm timeline now? 450mm has been an industry hot-button topic for years, with progress slowly picking up momentum: SEMI's already done most of the standards work, and many equipment makers are finally coming out with "450mm tools" (some simple retrofits, some far more complicated), including pledges of millions of dollars for 450mm tool development much of which could be for continued feasibility studies. Originally the Intel/TSMC/Samsung triumverate wanted a 450mm pilot line by 2012, but almost certainly that won't happen now, and this new consortium's five-year pledge suggests as much, and even TSMC's proposed timeline looks a bit optimistic at this point. Gartner research VP Bob Johnson predicts prototype process tools might be installed sometime in 2012, with functional processes two years after that and an official pilot line in ~2015, then another two years for "the first real production" on 450mm wafers in 2017-2019.
The problems for 450mm remain twofold: uncertain returns and competing priorities. Chipmakers believe that 450mm wafer manufacturing is their next big stepdown cost reduction (~30%). Equipment makers bellyached about 450mm, remembering their extended and not-so-profitable 200mm-to-300mm transition (and they're hesitant to now spend lots of R&D for a technology that will basically shrink their own market by 30%), but lately they have been more publicly supportive of it. An actual 450 pilot line, with tools configured in a manufacturing environment and producing patterned 450mm wafers, will go a long way toward getting everyone on the same page about what to expect.
But the industry arguably has other important technology concerns besides the economics-based 450mm transition. Leading-edge chipmakers have managed to keep extending optical lithography with immersion, multiple patterning, etc., but the next year or two likely will see the (attempted) introduction of EUV litho into manufacturing, and possibly other next-gen litho technologies, mixed as-needed with other flavors of optical litho. And note that a 2015 450mm pilot line coincides with what is expected to be the 10nm node at leading edge, and 2017-2019 could be 7nm or even 5nm. How many more nodes will conventional silicon continue to be viable, necessitating any of a range of alternatives, from known materials to exotic ones (e.g. graphene or nanotubes)? -- J.M.