Demands on the Cloud, data center; Wally Rhines' 3D IC roadmap

Sharon Holt, SVP/GM, Semiconductor Business Group at Rambus, cited some interesting information during her presentation at the GSA Memory Conference (3/31/11, San Jose, CA). For example: the cost of a 22nm logic IC design is >$140M – for each new design. And from Cisco’s Global Mobile Data Traffic Forecast update – Holt presented the following data for consideration on the demands on the Cloud: 1) In 2010, global mobile data traffic was up 159%; 2) smart phones are 13% of the global installed base, yet drive 78% of the total traffic; 3) so far, video represents >50% of all mobile traffic in 2011; 4) and the average tablet traffic is 5X that of smart phones, which are 24X that of feature phones. Watch for my upcoming podcast interview with Holt on the search for a unified memory solution (i.e., one that works for PCs/servers, and for smart phones/tablets).


And in his presentation at the GSA Memory Conference, Jim Elliot, VP, Memory Marketing & Product Planning at Samsung Semiconductor, tackled the power consumption challenges of the data center. He said a Web 3.0 impact on traffic load study indicates that by 2015, 1266PB of memory will be required by data centers. 1PB = 13.3 years of HD video. And data center power consumption is growing. Elliot noted that data centers account for 23% of global ICT power consumption (about 1% of total worldwide power) and growing. SSDs can help address the challenge because of course, they have no moving parts, thus, use less power. “One SSD can replace up to 20 15k HDDs,” said Elliot. “An SSD outperforms an HDD by 47X in IOPS.” (Debra Vogler)


The 3D IC roadmap according to Mentor Graphics
Wally Rhines, chairman & CEO of Mentor Graphics, outlined what he considers to be a realistic 3D IC roadmap at the GSA Memory Conference (3/31/11, San Jose, CA). Today, there are sensors on logic, limited volume stacked memories, and PoP and flip-chip memories on processors. In the next 2-3 years, the technology will move to what Rhines calls 2.5D+. It comprises a rapidly increasing use of interposers, the integration of logic and memory with flip-chip and interposers, and mixed analog, RF, logic and memory in multi-die stacks, and TSVs outside the active circuitry. In 5 or more years from now, Rhines sees the industry at full 3D with embedded TSVs in leading edge logic chips. (Debra Vogler)