Common Platform alliance to use gate last at 20nm

At today's Common Platform Tech Forum event (Santa Clara, CA), Dr. Gary Patton, VP, IBM Semiconductor R&D Center, told attendees that the alliance will switch from a gate first approach to gate last at 20nm. He noted that 20nm technology demands different requirements than 28nm. He said both approaches have been evaluated in parallel since 2001 and stated that he is less concerned with the replacement gate process than he is about the other innovations that will be needed at 20nm (e.g., self-aligned contacts, local interconnects, and BEOL pitches).

The time frame for introduction of 20nm is 1Q2013 for early production. It is anticipated that third generation ArF immersion with double-patterning and source/mask optimization (SMO) will be used at 20nm.