How fabless works for MEMS: A chat with InvenSense’s VP of business development

July 31, 2012 -- Jengyaw "Joseph" Jiang, VP of business development, InvenSense Inc. (NYSE:INVN), spoke with Solid State Technology about the company’s fabless approach to micro electro mechanical system (MEMS) innovation and its Nasiri-Fabrication (NF)-Shuttle, which launched in 2012 and will soon do a third run.

Photo. Joseph Jiang, InvenSense.

The NF Platform integrates CMOS and MEMS on silicon. The InvenSense NF Platform has been used to produce over 200 million MEMS units to date.

NF-Shuttle allows where mask costs to be split amongst multiple users that purchase real estate on the same mask. The users can validate designs on silicon with a much lower upfront cost than prototyping on their own. InvenSense launched the first shuttle run in January 2012 with select universities, including Stanford University and University of California Berkeley (UC Berkeley). Its second run occurred in May, and the company is currently preparing for a third in December. Stanford and UC Berkeley secured spots on both of these additional shuttles.

Figure. InvenSense's NF Platform.
(Click the image to enlarge.)

The December shuttle is the first that will be opened up to the industry at large. “Opening our proprietary MEMS fabrication process to industry and universities benefits the whole MEMS industry,” said Jiang. The platform can be used for pressure sensors, accelerometers, microphones, etc. It is very difficult to develop MEMS currently, with the 1 product/1 process model, Jiang noted.

As a fabless company, InvenSense works with multiple foundries (GLOBALFOUNDRIES and TSMC) to produce its MEMS devices. This combines fairly standard, high-volume manufacturing processes with innovation in the MEMS design. By sharing the shuttle with other MEMS developers, InvenSense expects the participants to have lower engineering costs and gain access to top-tier foundries. Smaller MEMS companies often work with smaller foundries, which cannot be cost-competitive with the top-tier foundries, nor offer the same capacity, Jiang said. InvenSense benefits by having its manufacturing platform gain adoption throughout the MEMS industry, and licensing it to other MEMS makers.

The fabless model also frees InvenSense from some of the worries about disruptions, such as those from natural disasters, slamming its supply chain to a halt. This is a clear advantage in the semiconductor space, which we are applying to MEMS, Jiang said.

MEMS have always had to compete on cost, size, and performance, much like semiconductors. As MEMS hit milestones in these areas, volumes are steadily increasing. In the future, securing foundry capacity in larger wafer sizes with high yielding processes will need to be a primary goal of MEMS makers.

-- Meredith Courtemanche, digital media editor, meredithc@pennwell.com

What does healthcare have to do with semiconductors?

July 13, 2012 -- SEMICON West, which just wrapped in San Francisco, CA, gathers all things semiconductor R&D and manufacturing. So why was healthcare such a popular topic at the show? From research organizations (imec, CEA-Leti) to industry roadmappers (ITRS), semiconductor-focused groups are looking at ways to improve healthcare. The refrain that today's healthcare system is unsustainable echoed through many sessions. The semiconductor industry sees plenty of engineering solutions to the healthcare problem.

"We cannot continue with the medical system as it is today" -- Patrick Cogez, ITRS.

The International Technology Roadmap for Semiconductors (ITRS) 2012 update included a new focus on semiconductor device applications, one of which was healthcare. Semiconductors and micro electro mechanical systems (MEMS) offer patient care and health monitoring at home, at a vastly lower cost than hospitalization. Read more about ITRS's applications focus, in partnership with iNEMI, here.

"Semiconductors can change the landscape of modern medicine" -- Andrew Thompson, Proteus Digital Health, imec panel discussion

At the imec Technology Forum co-located with SEMICON West, several speakers looked at the cost of healthcare, our increased lifespans, and different diseases and disease mechanisms (how viruses spread, the needs of chronically ill patients, etc). What options does the semiconductor industry offer? Diagnostic tools today are relatively low tech, and generally captive in a hospital, said Serge Biesemans, VP of wafer technology and smart systems, imec. Microfluidic lab-on-a-chip wafers allow nearly instant analysis for virus and cancer detection, among other uses. With multiplexing on a wafer and advanced microscopy, diseases can be detected earlier. The semiconductor industry can apply its vast experience with Moore's Law to make these tools fast, small, cheap, and accurate, releasing diagnostics from the hospital into doctor's offices and homes.

Sensor technology is evolving to allow health "predictions," much like we predict the weather today. We need to move from reactive healthcare to predictive, and sensors are the conduit, imec argues. MEMS-based sensors that are cheap and portable can produce readings comparable in accuracy to expensive medical equipment and procedures like indirect calorimetry. MEMS, thin-film, and CMOS image sensors under development at imec can analyze sweat, breath, stress, pain, and the composition of skin, to name a few applications.

Thompson, CEO of Proteus Digital Health, spoke about the edible semiconductor concept, where patients swallow a semiconductor "pill" that then sends data to a smartphone. We need to eliminate the doctor, nurse, and hospital building in our thinking about healthcare, he asserted. The technology exists to track medicine intake, sleep, social behavior, and other factors in a patient’s life. And this technology is non-intrusive -- as easy as swallowing a pill or applying a band-aid. Through semiconductor and sensor technologies, we can prevent drastic, expensive medical interventions, like diabetes-related amputations.

All this led up to imec's concept for a cross-disciplinary consortia, from wafer fab to bio lab. imec's vision is to bring together semiconductor stakeholders -- fabless companies, wafer fabs, tool and materials suppliers -- with medical/healthcare stakeholders -- instrument makers, biologists, materials developers, etc.

"The next big thing for semiconductors is healthcare and medical technologies" -- Laurent Malier, Leti.
CEA-Leti develops middle-term research projects on transistor technologies. The work these researchers are doing to enable super computing, photonics and electronics integration, and ubiquitous sensors could be of enormous benefit to medical electronics, said Malier, Leti's CEO. He told me during CEA-Leti's research updates (check out highlights of CEA-Leti's research here) that he expects to be talking a lot about healthcare and medical technologies at SEMICON West next year. Many semiconductor industry professionals have an ah-ha! moment when they learn about the technological needs in medicine, Malier said, because they never considered the two fields to be related before.
In none of these presentations was the political side of healthcare directly addressed, beyond discussions of the cost of care today. In true semiconductor engineering fashion, these research and roadmapping groups see a problem and envision a technological solution.

-- Meredith Courtemanche, digital media editor, meredithc@pennwell.com

Comments:
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The energy behind energy at SEMICON West

July 11, 2012 -- SEMICON West opened yesterday with a keynote by Shekhar Y. Borkar, Intel Fellow and director of extreme-scale technologies at Intel Corporation. Borkar focused on the energy demands of ubiquitous computing, and how technologies developed for super computers will later be adopted into smartphones. The energy demands of today's transistors, Borkar says, will not be sustainable at the exaflop data rate. At CEA-Leti's presentations later that day, researchers agreed. So how can we achieve a new power consumption paradigm?

Different transistor-level technologies can address reducing power consumption. Borkar shared Intel's 22nm 3D trigate transistor and voltage scaling at the circuit level. Scaling down the power supply voltage enables higher energy efficiency. He also discussed near-threshold voltage (NTV) operation, because energy efficiency peaks at the transistor's threshold voltage. Intel's trigate design reduces the required supply voltage and can be tuned for different thresholds. Intel has developed an experimental NTV processor to demonstrate this work. Get a look inside the trigate transistor in blogger Dick James' Intel's 22nm trigate transistor exposed

Borkar also discussed the use of systems on chip (SoC) for targeted efficiency and flexibility -- using single-purpose blocks that are extremely energy efficient along with the flexible blocks, such as microprocessor transistors, to make a chip accomodate various operations. Borkar calls this "valued performance."

Other energy-saving device architectures include stacking DRAM memory with a logic buffer to direct access to a specific page. Intel is developing this concept with Micron, calling it a Hybrid Memory Cube. Learn more from blogger Dr. Phil Garrou's The Micron Memory Cube consortium
Finally, Borkar shared some unconventional interconnect strategies for package-to-system energy savings, such as top-of-package interconnect. He stressed that circuits and interconnects should be co-optimized to maximize energy efficiency.

At CEA-Leti's research meeting, Hughes Metras, VP of strategic partnerships in North America, also projected that the next step in super computing, exascale, would be insupportably energy intensive. Leti's solutions to the energy and bandwidth demands of future computing include a planar fully depleted silicon on insulator (FDSOI) transistor architecture, silicon photonics for light-based data communication rather than electrical, and 3D integration for lower-loss and shorter interconnects.

Maud Vinet, Leti assignee at IBM, focused on planar FDSOI transistors. The benefit of planar technology is that we already have the major of the wafer processing technologies we need from bulk CMOS. The biggest change is that planar FDSOI uses extremely thin (a couple nanometers) silicon films, so extra attention must be paid at any step where silicon could be lost. The smaller gate lengths of planar FDSOI prevent parasitics, for faster operation. Back bias allows the device's threshold voltage to be tuned, a concept discussed during Intel's keynote as well. Other elements -- strain on the NFET, silicon germanium (SiGe) for the PFET -- combine in the planar FDSOI to enable 30% less power dissipation, or wasted energy, than bulk transistors.

We'll have more information from CEA-Leti's research presentatons, including the design and manufacturing perspectives on 2.5D/3D integration, on the Solid State Technology website, with a series of video interviews with the researchers. Also watch for a video interview with Intel's Borkar summarizing his keynote's main points. You'll find it all in Solid State Technology’s coverage of SEMICON West 2012.
 
-- Meredith Courtemanche, digital media editor, meredithc@pennwell.com

SEMICON West buzz: Curtains up for 450mm wafers

July 10, 2012 -- In the pre-show conferences and press releases leading up to SEMICON West, 450mm wafer development is getting a lot of attention.



Research organization imec received a major government investment to build a 450mm cleanroom. I spoke with imec president and CEO Luc Van den hove about the 450mm announcement.



ASML launched a program wherein customers can buy minority stakes in the tool maker, which will fund EUV lithography and 450mm development. Intel is the first taker with a 15% share in ASML.



KLA-Tencor installed its first process control systems for handling and inspecting unpatterned 450mm wafers, the automated Surfscan SP3 450 defect and surface quality characterization tool. KLA-Tencor says it has received multiple orders for its SP3 450mm-capable tool and shipped several systems (imec is using one).



CyberOptics came out with a 450mm version of its WaferSense Auto Vibration System, AVS450. The product is a wireless wafer-life vibration monitoring device that travels through the entire path of a wafer to measure vibrations of wafer transfers in x, y and z dimensions during semiconductor processes and fabrications and report real-time acceleration data in three axes for engineers to identify vibration anomalies during wafer processing.



This is just a sampling of what is sure to be a week filled with 450mm discussions. 450mm development has been waiting in the wings for a long time. If the pre-SEMICON West buzz is to be believed, now is its time to take center stage.



SEMICON West 2012, http://www.semiconwest.org/, opens in just a few hours in the Moscone Center in San Francisco, CA. My first event will be today's keynote, "Ubiquitous Computing in the Coming Years--Technology Challenges and Opportunities" by Intel's Shekhar Y. Borkar. See you there!


Stay on top of all the news and new product announcements from the show with our SEMICON West Channel, http://www.electroiq.com/semicon_west_2012.html



--Meredith Courtemanche, digital media editor, meredithc@pennwell.com

Twitter: @solid_statetech